Electrostatic discharge (ESD) can damage integrated circuits. ESD can occur when a human touches an integrated circuit, when the integrated circuit contacts a machine or when the integrated circuit contacts a package in which the integrated circuit is packaged.
ESD can dramatically reduce the yield of integrated circuits. In order to reduce the affect of ESD events various ESD protections circuits were developed. The ESD protection circuits include snap-back ESD protection circuits, non snap-back ESD protection circuits, and the like. Pad based ESD protection circuits as well as rail-based ESD protection circuits were also developed. Different ESD protection circuits can have different response patterns.
Various ESD protection circuits and methods, as well as some prior art ESD testing methods are illustrated in the following articles, patents and patent applications, all being incorporated herein by reference: “ESD test methods on integrated circuits: an overview”, M. D. Ker, J. J. Peng and H. C. Jiang, ICECS 2001, 8th IEEE International conference on Electronics and Systems, pg. 1011-1014, vol. 2; “Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies”, M. Stockinger, J. Miller, M. Khazhinsky, C. Torres, J. Weldon, B. Preble, M. Akers, EOS/ESD Symposium proceedings 2003; U.S. Pat. No. 6,469,536 of Kessler at al.; U.S. Pat. No. 5,978,197 of Chan; U.S. Pat. No. 6,586,266 of Lin; U.S. patent application publication serial number 2002/0145432 of Allard. Jr. et al.; U.S. Pat. No. 6,906,386 of Williams et al. and PCT patent application publication serial number WO95/08124.
Many ESD testing methods include applying a high voltage signal to an integrated circuit. The high voltage can damage integrated circuit components and cause the defective integrated circuit components to emit infrared radiation. The infrared radiation can be detected by an infrared microscope. The appliance of high-voltage does not enable to accurately measure signals from the integrated circuit while the high voltage signals is applied to it.
Various prior art ESD testing methods include causing an electrical arc discharge between the integrated circuit and the testing device. This arc cannot be accurately repeated, thus a large number of tests can be required.
There is a need to provide a device and method for efficiently evaluating electrostatic discharge (ESD) protection capabilities of an integrated circuit.